Samsung said in a statement that the 3-nanometer chips were based on Gate-All-Around (GAA) technology, which the tech firm said can cut power consumption by up to 45 percent, improve performance by 23 percent and reduce the area by 16 percent compared to the 5-nanometer process.
The second-generation 3-nanometer process will lower power consumption by up to 50 percent, improve performance by 30 percent and reduce the area by 35 percent, according to Samsung.
"We seek to continue this leadership with the world's first 3-nm process," said Choi Siyoung, president and head of foundry business at Samsung Electronics.
"We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology," Choi noted.
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